MC9S12XD256MAL Datasheet, PDF (827/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.3 Port A Data Direction Register (DDRA)
R
W
Reset
7
DDRA7
0
6
DDRA6
5
DDRA5
4
DDRA4
3
DDRA3
2
DDRA2
0
0
0
0
0
Figure 22-5. Port A Data Direction Register (DDRA)
1
DDRA1
0
0
DDRA0
0
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 22-6. DDRA Field Descriptions
Field
Description
7–0
DDRA[7:0]
Data Direction Port A — This register controls the data direction for port A. When Port A is operating as a general
purpose I/O port, DDRA determines whether each pin is an input or output. A logic level “1” causes the
associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PORTA after changing the DDRA register.
22.3.2.4 Port B Data Direction Register (DDRB)
R
W
Reset
7
DDRB7
0
6
DDRB6
5
DDRB5
4
DDRB4
3
DDRB3
2
DDRB2
0
0
0
0
0
Figure 22-6. Port B Data Direction Register (DDRB)
1
DDRB1
0
0
DDRB0
0
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data are read from this register.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 22-7. DDRB Field Descriptions
Field
Description
7–0
DDRB[7:0]
Data Direction Port B — This register controls the data direction for port B. When Port B is operating as a general
purpose I/O port, DDRB determines whether each pin is an input or output. A logic level “1” causes the
associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PORTB after changing the DDRB register.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
829