MC9S12XD256MAL Datasheet, PDF (356/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
CLK1
CLK0
4:1 MUX
TIMCLK (Timer Clock)
Prescaled Clock
(PCLK)
Interrupt
Clock Select
(PAMOD)
Edge Detector
P7
8-Bit PAC3
(PACN3)
8-Bit PAC2
(PACN2)
PACA
Interrupt
MUX
Divide by 64
Bus Clock
8-Bit PAC1
(PACN1)
8-Bit PAC0
(PACN0)
PACB
Delay Counter
Edge Detector
P0
Figure 7-70. 16-Bit Pulse Accumulators Block Diagram
Px
Edge
Detector
Delay
Counter
16-Bit Main Timer
TCx Input
Capture Register
Set CxF
Interrupt
TCxH I.C.
Holding Register
BUFEN • LATQ • TFMOD
Figure 7-71. Block Diagram for Port 7 with Output Compare/Pulse Accumulator A
MC9S12XDP512 Data Sheet, Rev. 2.21
356
Freescale Semiconductor