MC9S12XD256MAL Datasheet, PDF (565/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 14 Voltage Regulator (S12VREG3V3V5)
14.4.2.2 Reduced Power Mode
In Reduced Power Mode, the gate of the output transistor is connected directly to a reference voltage to
reduce power consumption.
14.4.3 Low-Voltage Detect (LVD)
Subblock LVD is responsible for generating the low-voltage interrupt (LVI). LVD monitors the input
voltage (V_DDA–V_SSA) and continuously updates the status flag LVDS. Interrupt flag LVIF is set whenever
status flag LVDS changes its value. The LVD is available in FPM and is inactive in Reduced Power Mode
or Shutdown Mode.
14.4.4 Power-On Reset (POR)
This functional block monitors V_DD. If V_DD is below V_PORD, POR is asserted; if V_DD exceeds V_PORD,
the POR is deasserted. POR asserted forces the MCU into Reset. POR Deasserted will trigger the power-on
sequence.
14.4.5 Low-Voltage Reset (LVR)
Block LVR monitors the primary output voltage V_DD. If it drops below the assertion level (V_LVRA) signal,
LVR asserts; if V_DD rises above the deassertion level (V_LVRD) signal, LVR deasserts. The LVR function
is available only in Full Performance Mode.
14.4.6 Regulator Control (CTRL)
This part contains the register block of VREG_3V3 and further digital functionality needed to control the
operating modes. CTRL also represents the interface to the digital core logic.
14.4.7 Autonomous Periodical Interrupt (API)
Subblock API can generate periodical interrupts independent of the clock source of the MCU. To enable
the timer, the bit APIFE needs to be set.
The API timer is either clocked by a trimmable internal RC oscillator or the bus clock. Timer operation
will freeze when MCU clock source is selected and bus clock is turned off. See CRG specification for
details. The clock source can be selected with bit APICLK. APICLK can only be written when APIFE is
not set.
The APIR[11:0] bits determine the interrupt period. APIR[11:0] can only be written when APIFE is
cleared. As soon as APIFE is set, the timer starts running for the period selected by APIR[11:0] bits. When
the configured time has elapsed, the flag APIF is set. An interrupt, indicated by flag APIF = 1, is triggered
if interrupt enable bit APIE = 1. The timer is started automatically again after it has set APIF.
The procedure to change APICLK or APIR[11:0] is first to clear APIFE, then write to APICLK or
APIR[11:0], and afterwards set APIFE.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
565