MC9S12XD256MAL Datasheet, PDF (958/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
23.0.5.69 Port AD1 Data Direction Register 1 (DDR1AD1)
7
6
5
4
3
2
1
R
DDR1AD115 DDR1AD114 DDR1AD113 DDR1AD112 DDR1AD111 DDR1AD110 DDR1AD19
W
0
DDR1AD18
Reset
0
0
0
0
0
0
0
0
Figure 23-71. Port AD1 Data Direction Register 1 (DDR1AD1)
Read: Anytime.
Write: Anytime.
This register configures pins PAD as either input or output.
Table 23-62. DDR1AD1 Field Descriptions
Field
Description
7–0
DDR1AD1[15:8]
Data Direction Port AD1 Register 1
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is
read on PTAD11 register, when changing the DDR1AD1 register.
Note: To use the digital input function on port AD1 the ATD1 digital input enable register (ATD1DIEN1) has
to be set to logic level “1”.
23.0.5.70 Port AD1 Reduced Drive Register 0 (RDR0AD1)
7
6
5
4
3
2
1
0
R
RDR0AD123 RDR0AD122 RDR0AD121 RDR0AD120 RDR0AD119 RDR0AD118 RDR0AD117 RDR0AD116
W
Reset
0
0
0
0
0
0
0
0
Figure 23-72. Port AD1 Reduced Drive Register 0 (RDR0AD1)
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each PAD[23:16] output pin as either full or reduced. If the
port is used as input this bit is ignored.
Table 23-63. RDR0AD1 Field Descriptions
Field
Description
7–0
Reduced Drive Port AD1 Register 0
RDR0AD1[23:16] 0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
MC9S12XDP512 Data Sheet, Rev. 2.21
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