MC9S12XD256MAL Datasheet, PDF (267/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

OR
Logical OR
Chapter 6 XGATE (S12XGATEV2)
OR
Operation
RS1 | RS2 ⇒ RD
RD | IMM16⇒ RD (translates to ORL RD, #IMM16[7:0]; ORH RD, #IMM16[15:8]
Performs a bit wise logical OR between two 16 bit values and stores the result in the destination
register RD.
CCR Effects
NZVC
∆ ∆ 0—
N: Set if bit 15 of the result is set; cleared otherwise.
Z: Set if the result is $0000; cleared otherwise.
Refer to ORH instruction for #IMM16 operations.
V: 0; cleared.
C: Not affected.
Code and CPU Cycles
Source Form
OR RD, RS1, RS2
OR RD, #IMM16
Address
Mode
TRI
IMM8
IMM8
00010
10100
10101
Machine Code
Cycles
RD
RS1
RS2 1 0
P
RD
IMM16[7:0]
P
RD
IMM16[15:8]
P
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
267