MC9S12XD256MAL Datasheet, PDF (957/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

23.0.5.67 Port AD1 Data Register 1 (PT1AD1)
7
R
PT1AD115
W
Reset
0
6
5
4
3
2
PT1AD114 PT1AD113 PT1AD112 PT1AD111 PT1AD110
0
0
0
0
0
Figure 23-69. Port AD1 Data Register 1 (PT1AD1)
1
PT1AD19
0
0
PT1AD18
0
Read: Anytime.
Write: Anytime.
This register is associated with AD1 pins PAD[15:8]. These pins can also be used as general
purpose I/O.
If the data direction bits of the associated I/O pins are set to 1, a read returns the value of the port
register, otherwise the value at the pins is read.
23.0.5.68 Port AD1 Data Direction Register 0 (DDR0AD1)
7
6
5
4
3
2
1
0
R
DDR0AD123 DDR0AD122 DDR0AD121 DDR0AD120 DDR0AD119 DDR0AD118 DDR0AD117 DDR0AD116
W
Reset
0
0
0
0
0
0
0
0
Figure 23-70. Port AD1 Data Direction Register 0 (DDR0AD1)
Read: Anytime.
Write: Anytime.
This register configures pin PAD[23:16] as either input or output.
Table 23-61. DDR0AD1 Field Descriptions
Field
Description
7–0
DDR0AD1[23:16]
Data Direction Port AD1 Register 0
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is
read on PTAD10 register, when changing the DDR0AD1 register.
Note: To use the digital input function on Port AD1 the ATD1 digital input enable register (ATD1DIEN0) has
to be set to logic level “1”.