MC9S12XD256MAL Datasheet, PDF (82/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 2 Clocks and Reset Generator (S12CRGV6)
2.2 External Signal Description
This section lists and describes the signals that connect off chip.
2.2.1 V_DDPLL and V_SSPLL — Operating and Ground Voltage Pins
These pins provide operating voltage (V_DDPLL) and ground (V_SSPLL) for the PLL circuitry. This allows
the supply voltage to the PLL to be independently bypassed. Even if PLL usage is not required, V_DDPLL
and V_SSPLL must be connected to properly.
2.2.2 XFC — External Loop Filter Pin
A passive external loop filter must be placed on the XFC pin. The filter is a second-order, low-pass filter
that eliminates the VCO input ripple. The value of the external filter network and the reference frequency
determines the speed of the corrections and the stability of the PLL. Refer to the device specification for
calculation of PLL Loop Filter (XFC) components. If PLL usage is not required, the XFC pin must be tied
to V_DDPLL.
V_DDPLL
MCU
XFC
C_S
C_P
R_S
Figure 2-2. PLL Loop Filter Connections
2.2.3 RESET — Reset Pin
RESET is an active low bidirectional reset pin. As an input. it initializes the MCU asynchronously to a
known start-up state. As an open-drain output, it indicates that a system reset (internal to the MCU) has
been triggered.
2.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the CRG.
MC9S12XDP512 Data Sheet, Rev. 2.21
82
Freescale Semiconductor