MC9S12XD256MAL Datasheet, PDF (327/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
7.3.2.11 Timer System Control Register 2 (TSCR2)
7
6
5
4
R
0
0
0
TOI
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
TCRE
0
2
PR2
0
1
PR1
0
0
PR0
0
Figure 7-16. Timer System Control Register 2 (TSCR2)
Read or write: Anytime
All bits reset to zero.
Table 7-14. TSCR2 Field Descriptions
Field
7
TOI
3
TCRE
2:0
PR[2:0]
Description
Timer Overflow Interrupt Enable
0 Timer overflow interrupt disabled.
1 Hardware interrupt requested when TOF flag set.
Timer Counter Reset Enable — This bit allows the timer counter to be reset by a successful channel 7 output
compare. This mode of operation is similar to an up-counting modulus counter.
0 Counter reset disabled and counter free runs.
1 Counter reset by a successful output compare on channel 7.
Note: If register TC7 = 0x0000 and TCRE = 1, then the TCNT register will stay at 0x0000 continuously. If register
TC7 = 0xFFFF and TCRE = 1, the TOF flag will never be set when TCNT is reset from 0xFFFF to 0x0000.
Timer Prescaler Select — These three bits specify the division rate of the main Timer prescaler when the PRNT
bit of register TSCR1 is set to 0. The newly selected prescale factor will not take effect until the next synchronized
edge where all prescale counter stages equal zero. See Table 7-15.
Table 7-15. Prescaler Selection
PR2
PR1
PR0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Prescale Factor
1
2
4
8
16
32
64
128
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
327