MC9S12XD256MAL Datasheet, PDF (1006/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
Table 24-28. PTM Field Descriptions (continued)
Field
3–2
PTM[3:2]
1–0
PTM[1:0]
Description
The routed CAN0 function (TXCAN0 and RXCAN0) takes precedence over the routed SPI0 and the general
purpose I/O function if the routed CAN0 module is enabled. Refer to MSCAN section for details.
The routed SPI0 function (SS0 and MISO0) takes precedence of the general purpose I/O function if the routed
SPI0 is enabled and not in bidirectional mode. Refer to SPI section for details.
The CAN0 function (TXCAN0 and RXCAN0) takes precedence over the general purpose I/O function if the CAN0
module is enabled. Refer to MSCAN section for details.
24.0.5.27 Port M Input Register (PTIM)
7
R PTIM7
6
PTIM6
5
PTIM5
4
PTIM4
3
PTIM3
2
PTIM2
1
PTIM1
0
PTIM0
W
Reset¹
—
—
—
—
—
—
—
—
= Unimplemented or Reserved
Figure 24-29. Port M Input Register (PTIM)
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
associated pin values.
Read: Anytime.
Write: Never, writes to this register have no effect.
This register always reads back the buffered state of the associated pins. This can also be used to detect
overload or short circuit conditions on output pins.
24.0.5.28 Port M Data Direction Register (DDRM)
7
R
DDRM7
W
6
DDRM6
5
DDRM5
4
DDRM4
3
DDRM3
2
DDRM2
1
DDRM1
0
DDRM0
Reset
0
0
0
0
0
0
0
0
Figure 24-30. Port M Data Direction Register (DDRM)
Read: Anytime.
Write: Anytime.
This register configures each port M pin as either input or output.
The CAN forces the I/O state to be an output for each port line associated with an enabled output
(TXCAN). It also forces the I/O state to be an input for each port line associated with an enabled input
(RXCAN). In those cases the data direction bits will not change.
1008
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor