MC9S12XD256MAL Datasheet, PDF (839/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.19 Port T Data Direction Register (DDRT)
R
W
Reset
7
DDRT7
0
6
DDRT6
5
DDRT5
4
DDRT4
3
DDRT3
2
DDRT2
0
0
0
0
0
Figure 22-21. Port T Data Direction Register (DDRT)
1
DDRT1
0
0
DDRT0
0
Read: Anytime.
Write: Anytime.
This register configures each port T pin as either input or output.
The ECT forces the I/O state to be an output for each timer port associated with an enabled output compare.
In this case the data direction bits will not change.
The DDRT bits revert to controlling the I/O direction of a pin when the associated timer output compare
is disabled.
The timer input capture always monitors the state of the pin.
Table 22-23. DDRT Field Descriptions
Field
Description
7–0
DDRT[7:0]
Data Direction Port T
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PTT or PTIT registers, when changing the DDRT register.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
841