MC9S12XD256MAL Datasheet, PDF (859/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

22.3.2.46 Port H Data Register (PTH)
Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
R
W
Routed
SPI
Reset
7
PTH7
SS2
0
6
PTH6
5
PTH5
4
PTH4
3
PTH3
2
PTH2
SCK2
MOSI2
MISO2
SS1
SCK1
0
0
0
0
0
Figure 22-48. Port H Data Register (PTH)
1
PTH1
MOSI1
0
0
PTH0
MISO1
0
Read: Anytime.
Write: Anytime.
Port H pins 7–0 are associated with the SCI4 and SCI5 as well as the routed SPI1 and SPI2 modules.
These pins can be used as general purpose I/O when not used with any of the peripherals.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the
port register, otherwise the buffered pin input state is read.
The routed SPI2 function takes precedence over the SCI4 and SCI5 and the general purpose I/O function
if the routed SPI2 module is enabled. Refer to SPI section for details.
The routed SPI1 function takes precedence over the general purpose I/O function if the routed SPI1 is
enabled. Refer to SPI section for details.
The SCI4 and SCI5 function takes precedence over the general purpose I/O function if the SCI4 or SCI5
is enabled. Refer to SCI section for details.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
861