MC9S12XD256MAL Datasheet, PDF (108/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 2 Clocks and Reset Generator (S12CRGV6)
Core req’s
Stop Mode.
Clear PLLSEL,
Disable PLL
Exit Stop w.
ext.RESET
Stop Mode left
due to external reset
Enter
Stop Mode
No
INT
No
Yes
PSTP=1
CME=1
No
?
?
?
Yes
Yes
SCME=1 & ^Yes
FSTWKP=1
?
No
No
CM fail
?
Yes
Exit Stop w. ^No
CMRESET
No
SCME=1
?
Yes
Exit
Stop Mode
Clock
OK
?
Exit Stop w.
no
CMRESET
Yes
Exit
Stop Mode
Exit
Stop Mode
Generate
SCM Interrupt
(Wakeup from Stop)
SCME=1
?
Yes
No
SCMIE=1
?
Yes
Exit
Stop Mode
Enter
SCM
Enter SCM
SCMIF not
set!
Enter
SCM
No
INT
?
Yes
Exit
Stop Mode
No
SCM=1
?
Yes
Enter
SCM
Continue w.
normal OP
Figure 2-22. Stop Mode Entry/Exit Sequence
MC9S12XDP512 Data Sheet, Rev. 2.21
108
Freescale Semiconductor