MC9S12XD256MAL Datasheet, PDF (1203/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

29.3.2.7 Flash Command Register (FCMD)
The FCMD register is the Flash command register.
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1)
7
6
5
4
3
2
1
0
R
0
W
CMDB
Reset
1
1
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 29-12. Flash Command Register (FCMD)
All CMDB bits are readable and writable during a command write sequence while bit 7 reads 0 and is not
writable.
Table 29-15. FCMD Field Descriptions
Field
Description
6:0
Flash Command — Valid Flash commands are shown in Table 29-16. Writing any command other than those
CMDB[6:0] listed in Table 29-16 sets the ACCERR flag in the FSTAT register.
Table 29-16. Valid Flash Command List
CMDB[6:0]
0x05
0x06
0x20
0x40
0x41
0x47
NVM Command
Erase Verify
Data Compress
Word Program
Sector Erase
Mass Erase
Sector Erase Abort
29.3.2.8 Flash Control Register (FCTL)
The FCTL register is the Flash control register.
7
R
0
6
NV6
5
NV5
4
NV4
3
NV3
2
NV2
1
NV1
0
NV0
W
Reset
0
F
F
F
F
F
F
F
= Unimplemented or Reserved
Figure 29-13. Flash Control Register (FCTL)
All bits in the FCTL register are readable but are not writable.
The FCTL NV bits are loaded from the Flash nonvolatile byte located at global address 0x7F_FF0E during
the reset sequence, indicated by F in Figure 29-13.
Freescale Semiconductor
MC9S12XDP512 Data Sheet, Rev. 2.21
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