MC9S12XD256MAL Datasheet, PDF (1122/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 27 512 Kbyte Flash Module (S12XFTX512K4V2)
The FCTL register is loaded from the Flash Configuration Field byte at global address 0x7F_FF0E during
the reset sequence, indicated by F in Figure 27-15.
Table 27-19. FCTL Field Descriptions
Field
7-0
NV[7:0]
Description
Non volatile Bits — The NV[7:0] bits are available as nonvolatile bits. Refer to the Device User Guide for proper
use of the NV bits.
27.3.2.9 Flash Address Registers (FADDR)
The FADDRHI and FADDRLO registers are the Flash address registers.
7
6
5
4
3
2
1
0
R
FADDRHI
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 27-16. Flash Address High Register (FADDRHI)
7
6
5
4
3
2
1
0
R
FADDRLO
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 27-17. Flash Address Low Register (FADDRLO)
All FADDRHI and FADDRLO bits are readable but are not writable. After an array write as part of a
command write sequence, the FADDR registers will contain the mapped MCU address written.
27.3.2.10 Flash Data Registers (FDATA)
The FDATAHI and FDATALO registers are the Flash data registers.
7
6
5
4
3
2
1
0
R
FDATAHI
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 27-18. Flash Data High Register (FDATAHI)
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MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor