MC9S12XD256MAL Datasheet, PDF (162/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
5.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the ATD.
5.3.1 Module Memory Map
Figure 5-2 gives an overview of all ATD registers.
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
5.3.2 Register Descriptions
This section describes in address order all the ATD registers and their individual bits.
Register
Name
ATDCTL0
ATDCTL1
ATDCTL2
ATDCTL3
ATDCTL4
ATDCTL5
ATDSTAT0
Unimplemente
d
ATDTEST0
ATDTEST1
Bit 7
6
5
4
3
2
1
Bit 0
R
0
0
0
0
0
WRAP2 WRAP1 WRAP0
W
R
0
0
0
0
ETRIGSEL
ETRIGCH2 ETRIGCH1 ETRIGCH0
W
R
ADPU
W
AFFC
AWAI ETRIGLE ETRIGP ETRIGE ASCIE
ASCIF
R
0
W
S8C
S4C
S2C
S1C
FIFO
FRZ1
FRZ0
R
SRES8
W
SMP1
SMP0
PRS4
PRS3
PRS2
PRS1
PRS0
R
0
DJM
DSGN
SCAN
MULT
W
CC
CB
CA
R
SCF
W
0
0
ETORF FIFOR
CC2
CC1
CC0
R
W
R
U
U
U
U
U
U
U
U
W
R
U
U
0
0
0
0
0
SC
W
= Unimplemented or Reserved
Figure 5-2. ATD Register Summary (Sheet 1 of 5)
MC9S12XDP512 Data Sheet, Rev. 2.21
162
Freescale Semiconductor