MC9S12XD256MAL Datasheet, PDF (253/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 6 XGATE (S12XGATEV2)
CPCH
Compare Immediate 8 bit Constant with
Carry (High Byte)
CPCH
Operation
RS.H - IMM8 - C ⇒ NONE, only condition code flags get updated
Subtracts the carry bit and the 8 bit constant IMM8 contained in the instruction code from the high byte of
the source register RD using binary subtraction and updates the condition code register accordingly. The
carry bit and Zero bits are taken into account to allow a 16 bit compare in the form of
CMPL
CPCH
BCC
R2,#LOWBYTE
R2,#HIGHBYTE
; branch condition
Remark: There is no equivalent operation using triadic addressing. Comparing the values of two registers
can be performed by using the subtract instruction with R0 as destination register.
CCR Effects
NZVC
∆∆∆∆
N: Set if bit 15 of the result is set; cleared otherwise.
Z: Set if the result is $00 and Z was set before this operation; cleared otherwise.
V: Set if a two´s complement overflow resulted from the operation; cleared otherwise.
RS[15] & IMM8[7] & result[15] | RS[15] & IMM8[7] & result[15]
C: Set if there is a carry from the bit 15 of the result; cleared otherwise.
RS[15] & IMM8[7] | RS[15] & result[15] | IMM8[7] & result[15]
Code and CPU Cycles
Source Form
CPCH RD, #IMM8
Address
Mode
IMM8
11011
Machine Code
RS
IMM8
Cycles
P
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
253