MC9S12XD256MAL Datasheet, PDF (487/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 11 Serial Communication Interface (S12SCIV5)
11.3.2.5 SCI Alternative Control Register 2 (SCIACR2)
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
= Unimplemented or Reserved
3
2
1
0
BERRM1 BERRM0
0
0
0
Figure 11-8. SCI Alternative Control Register 2 (SCIACR2)
Read: Anytime, if AMAP = 1
Write: Anytime, if AMAP = 1
0
BKDFE
0
Table 11-7. SCIACR2 Field Descriptions
Field
Description
2:1
Bit Error Mode — Those two bits determines the functionality of the bit error detect feature. See Table 11-8.
BERRM[1:0]
0
BKDFE
Break Detect Feature Enable — BKDFE enables the break detect circuitry.
0 Break detect circuit disabled
1 Break detect circuit enabled
BERRM1
0
0
1
1
Table 11-8. Bit Error Mode Coding
BERRM0
Function
0
Bit error detect circuit is disabled
1
Receive input sampling occurs during the 9th time tick of a transmitted bit
(refer to Figure 11-19)
0
Receive input sampling occurs during the 13th time tick of a transmitted bit
(refer to Figure 11-19)
1
Reserved
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
487