MC9S12XD256MAL Datasheet, PDF (1268/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Appendix A Electrical Characteristics
A.5.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL´s voltage controlled oscillator (VCO) is
also the system clock source in self clock mode.
A.5.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
C_p
V_DDPLL
C_s
R
Phase
XFC Pin
VCO
f_osc
1
f_ref
refdv+1
D
KF
f_vco
KV
Detector
fcmp
Loop Divider
1
1
synr+1
2
Figure A-3. Basic PLL Functional Diagram
The following procedure can be used to calculate the resistance and capacitance values using typical values
for K₁, f₁ and i_ch from Table A-23.
The grey boxes show the calculation for f_VCO = 80 MHz and f_ref = 4 MHz. For example, these frequencies
are used for f_OSC = 4-MHz and a 40-MHz bus clock.
The VCO gain at the desired VCO frequency is approximated by:
KV = K1 ⋅ e^{(---f--K1----1-–----⋅f--v-1--c-V---o----)}
= –195MHz ⁄ V ⋅ e1^{---2--–-6--1---–9---5-8---0-} = -154.0MHz/V
The phase detector relationship is given by:
K_Φ = – ich ⋅ KV = –3.5µA ⋅ (–154MHz ⁄ V) = 539.1Hz ⁄ Ω
i_ch is the current in tracking mode.
The loop bandwidth f_C should be chosen to fulfill the Gardner’s stability criteria by at least a factor of 10,
typical values are 50. ζ = 0.9 ensures a good transient response.
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MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor