MC9S12XD256MAL Datasheet, PDF (371/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)
NOTE
Register bits PCLK0 to PCLK7 can be written anytime. If a clock select is
changed while a PWM signal is being generated, a truncated or stretched
pulse can occur during the transition.
Table 8-3. PWMCLK Field Descriptions
Field
7
PCLK7
6
PCLK6
5
PCLK5
4
PCLK4
3
PCLK3
2
PCLK2
1
PCLK1
0
PCLK0
Description
Pulse Width Channel 7 Clock Select
0 Clock B is the clock source for PWM channel 7.
1 Clock SB is the clock source for PWM channel 7.
Pulse Width Channel 6 Clock Select
0 Clock B is the clock source for PWM channel 6.
1 Clock SB is the clock source for PWM channel 6.
Pulse Width Channel 5 Clock Select
0 Clock A is the clock source for PWM channel 5.
1 Clock SA is the clock source for PWM channel 5.
Pulse Width Channel 4 Clock Select
0 Clock A is the clock source for PWM channel 4.
1 Clock SA is the clock source for PWM channel 4.
Pulse Width Channel 3 Clock Select
0 Clock B is the clock source for PWM channel 3.
1 Clock SB is the clock source for PWM channel 3.
Pulse Width Channel 2 Clock Select
0 Clock B is the clock source for PWM channel 2.
1 Clock SB is the clock source for PWM channel 2.
Pulse Width Channel 1 Clock Select
0 Clock A is the clock source for PWM channel 1.
1 Clock SA is the clock source for PWM channel 1.
Pulse Width Channel 0 Clock Select
0 Clock A is the clock source for PWM channel 0.
1 Clock SA is the clock source for PWM channel 0.
8.3.2.4 PWM Prescale Clock Select Register (PWMPRCLK)
This register selects the prescale clock source for clocks A and B independently.
7
R
0
W
Reset
0
Read: Anytime
Write: Anytime
6
5
4
3
2
1
0
PCKB2
PCKB1
PCKB0
PCKA2
PCKA1
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-6. PWM Prescale Clock Select Register (PWMPRCLK)
0
PCKA0
0
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
371