MC9S12XD256MAL Datasheet, PDF (1211/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1)
29.4.2.1 Erase Verify Command
The erase verify operation will verify that a Flash block is erased.
An example flow to execute the erase verify operation is shown in Figure 29-23. The erase verify command
write sequence is as follows:
1. Write to a Flash block address to start the command write sequence for the erase verify command.
The address and data written will be ignored.
2. Write the erase verify command, 0x05, to the FCMD register.
3. Clear the CBEIF flag in the FSTAT register by writing a 1 to CBEIF to launch the erase verify
command.
After launching the erase verify command, the CCIF flag in the FSTAT register will set after the operation
has completed unless a new command write sequence has been buffered. The number of bus cycles
required to execute the erase verify operation is equal to the number of addresses in a Flash block plus 14
bus cycles as measured from the time the CBEIF flag is cleared until the CCIF flag is set. Upon completion
of the erase verify operation, the BLANK flag in the FSTAT register will be set if all addresses in the
selected Flash block are verified to be erased. If any address in a selected Flash block is not erased, the
erase verify operation will terminate and the BLANK flag in the FSTAT register will remain clear. The
MRDS bits in the FTSTMOD register will determine the sense-amp margin setting during the erase verify
operation.
Freescale Semiconductor
MC9S12XDP512 Data Sheet, Rev. 2.21
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