MC9S12XD256MAL Datasheet, PDF (507/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 11 Serial Communication Interface (S12SCIV5)
Figure 11-26 shows a burst of noise near the beginning of the start bit that resets the RT clock. The sample
after the reset is low but is not preceded by three high samples that would qualify as a falling edge.
Depending on the timing of the start bit search and on the data, the frame may be missed entirely or it may
set the framing error flag.
RXD
Start Bit
LSB
No Start Bit Found
Samples 1 1 1 1 1 1 1 1 1 0
0
1
100000000
RT Clock
RT Clock Count
Reset RT Clock
Figure 11-26. Start Bit Search Example 5
In Figure 11-27, a noise burst makes the majority of data samples RT8, RT9, and RT10 high. This sets the
noise flag but does not reset the RT clock. In start bits only, the RT8, RT9, and RT10 data samples are
ignored.
Start Bit
LSB
RXD
Samples 1 1 1 1 1 1 1 1 1 0
0
0
0101
RT Clock
RT Clock Count
Reset RT Clock
Figure 11-27. Start Bit Search Example 6
11.4.6.4 Framing Errors
If the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming frame, it
sets the framing error flag, FE, in SCI status register 1 (SCISR1). A break character also sets the FE flag
because a break character has no stop bit. The FE flag is set at the same time that the RDRF flag is set.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
507