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MC9S12XD256MAL Datasheet, PDF (456/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network | |||
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Chapter 10 Freescaleâs Scalable Controller Area Network (S12MSCANV3)
âMSCAN Control Register 0 (CANCTL0)â). In case of a transmission, the CPU can only read the time
stamp after the respective transmit buffer has been ï¬agged empty.
The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer
overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The
CPU can only read the time stamp registers.
R
W
Reset:
7
TSR15
x
6
TSR14
5
TSR13
4
TSR12
3
TSR11
2
TSR10
x
x
x
x
x
Figure 10-37. Time Stamp Register â High Byte (TSRH)
1
TSR9
x
0
TSR8
x
R
W
Reset:
7
TSR7
x
6
TSR6
5
TSR5
4
TSR4
3
TSR3
2
TSR2
x
x
x
x
x
Figure 10-38. Time Stamp Register â Low Byte (TSRL)
1
TSR1
x
0
TSR0
x
Read: Anytime when TXEx ï¬ag is set (see Section 10.3.2.7, âMSCAN Transmitter Flag Register
(CANTFLG)â) and the corresponding transmit buffer is selected in CANTBSEL (see Section 10.3.2.11,
âMSCAN Transmit Buffer Selection Register (CANTBSEL)â).
Write: Unimplemented
10.4 Functional Description
10.4.1 General
This section provides a complete functional description of the MSCAN. It describes each of the features
and modes listed in the introduction.
MC9S12XDP512 Data Sheet, Rev. 2.21
456
Freescale Semiconductor
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