MC9S12XD256MAL Datasheet, PDF (1024/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
24.0.5.61 Port AD1 Data Direction Register 1 (DDR1AD1)
7
R
DDR1AD17
W
6
DDR1AD16
5
DDR1AD15
4
DDR1AD14
3
DDR1AD13
2
DDR1AD12
1
DDR1AD11
0
DDR1AD10
Reset
0
0
0
0
0
0
0
0
Figure 24-63. Port AD1 Data Direction Register 1 (DDR1AD1)
Read: Anytime.
Write: Anytime.
This register configures pins PAD[7:0] as either input or output.
Table 24-55. DDR1AD1 Field Descriptions
Field
Description
7–0
DDR1AD1[7:0]
Data Direction Port AD1 Register 1
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is
read on PTAD11 register, when changing the DDR1AD1 register.
Note: To use the digital input function on port AD1 the ATD1 digital input enable register (ATD1DIEN1) has
to be set to logic level “1”.
24.0.5.62 Port AD1 Reduced Drive Register 0 (RDR0AD1)
7
6
5
4
3
2
1
R
RDR0AD115 RDR0AD114 RDR0AD113 RDR0AD112 RDR0AD111 RDR0AD110 RDR0AD19
W
0
RDR0AD18
Reset
0
0
0
0
0
0
0
0
Figure 24-64. Port AD1 Reduced Drive Register 0 (RDR0AD1)
Read: Anytime.
Write: Anytime.
This register configures the drive strength of each PAD[15:8] output pin as either full or reduced. If the
port is used as input this bit is ignored.
Table 24-56. RDR0AD1 Field Descriptions
Field
Description
7–0
Reduced Drive Port AD1 Register 0
RDR0AD1[15:8] 0 Full drive strength at output.
1 Associated pin drives at about 1/6 of the full drive strength.
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MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor