MC9S12XD256MAL Datasheet, PDF (830/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.9 Port E Data Register (PORTE)
7
R
PE7
W
Alt.
Func.
XCLKS
or
ECLKX2
Reset
0
6
PE6
MODB
or
TAGHI
0
5
PE5
MODA
or
RE
or
TAGLO
0
4
PE4
3
PE3
2
PE2
EROMCTL
or
R/W
ECLK
LSTRB
or
or
WE
LDS
0
0
0
1
PE1
0
PE0
IRQ
XIRQ
—¹
—¹
= Unimplemented or Reserved
Figure 22-11. Port E Data Register (PORTE)
1 _{These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the associated}
pin values.
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 22-12. PORTE Field Descriptions
Field
7–0
PE[7:0]
Description
Port E — Port E bits 7–0 are associated with external bus control signals and interrupt inputs. These include
mode select (MODB, MODA), E clock, double frequency E clock, Instruction Tagging High and Low (TAGHI,
TAGLO), Read/Write (R/W), Read Enable and Write Enable (RE, WE), Lower Data Select (LDS), IRQ, and XIRQ.
When not used for any of these specific functions, Port E pins 7–2 can be used as general purpose I/O and
pins 1–0 can be used as general purpose inputs.
If the data direction bits of the associated I/O pins are set to logic level “1”, a read returns the value of the port
register, otherwise the buffered pin input state is read.
Pins 6 and 5 are inputs with enabled pull-down devices while RESET pin is low.
Pins 7 and 3 are inputs with enabled pull-up devices while RESET pin is low.
MC9S12XDP512 Data Sheet, Rev. 2.21
832
Freescale Semiconductor