MC9S12XD256MAL Datasheet, PDF (1009/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

This register configures the output pins as wired-OR. If enabled the output is driven active low only
(open-drain). A logic level of “1” is not driven. It applies also to the CAN outputs and allows a
multipoint connection of several serial modules. This bit has no influence on pins used as inputs.
Table 24-33. WOMM Field Descriptions
Field
Description
7–0
Wired-OR Mode Port M
WOMM[7:0] 0 Output buffers operate as push-pull outputs.
1 Output buffers operate as open-drain outputs.
24.0.5.33 Module Routing Register (MODRR)
7
R
0
W
6
5
MODRR6¹ MODRR5
4
MODRR4
3
MODRR3
2
MODRR2
Reset
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 24-35. Module Routing Register (MODRR)
1. Register implemented, function disabled: Written values can be read back.
1
MODRR1
0
0
MODRR0
0
Read: Anytime.
Write: Anytime.
This register configures the re-routing of CAN0, CAN4, SPI0, SPI1 on alternative ports.
Table 24-34. Module Routing Summary
MODRR
Module
6543210
xxxxx00
xxxxx01
CAN0
xxxxx10
xxxxx11
xxx00xx
xxx01xx
CAN4
xxx10xx
xxx11xx
SPI0
SPI1
xx0xxxx
xx1xxxx
x0xxxxx
x1xxxxx
Related Pins
RXCAN
TXCAN
PM0
PM2
PM1
PM3
PM4
PJ6
PJ6
PM4
PM6
Reserved
PM5
PJ7
PJ7
PM5
PM7
MISO
MOSI
SCK
SS
PS4
PM2
PS5
PM4
PS6
PM5
PS7
PM3
PP0
PP1
PP2
PP3
PH0
PH1
PH2
PH3