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MC9S12XD256MAL Datasheet, PDF (372/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network | |||
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Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)
NOTE
PCKB2â0 and PCKA2â0 register bits can be written anytime. If the clock
pre-scale is changed while a PWM signal is being generated, a truncated or
stretched pulse can occur during the transition.
Table 8-4. PWMPRCLK Field Descriptions
Field
Description
6â4
Prescaler Select for Clock B â Clock B is one of two clock sources which can be used for channels 2, 3, 6, or
PCKB[2:0] 7. These three bits determine the rate of clock B, as shown in Table 8-5.
2â0
Prescaler Select for Clock A â Clock A is one of two clock sources which can be used for channels 0, 1, 4 or
PCKA[2:0] 5. These three bits determine the rate of clock A, as shown in Table 8-6.
s
Table 8-5. Clock B Prescaler Selects
PCKB2
0
0
0
0
1
1
1
1
PCKB1
0
0
1
1
0
0
1
1
PCKB0
0
1
0
1
0
1
0
1
Value of Clock B
Bus clock
Bus clock / 2
Bus clock / 4
Bus clock / 8
Bus clock / 16
Bus clock / 32
Bus clock / 64
Bus clock / 128
Table 8-6. Clock A Prescaler Selects
PCKA2
0
0
0
0
1
1
1
1
PCKA1
0
0
1
1
0
0
1
1
PCKA0
0
1
0
1
0
1
0
1
Value of Clock A
Bus clock
Bus clock / 2
Bus clock / 4
Bus clock / 8
Bus clock / 16
Bus clock / 32
Bus clock / 64
Bus clock / 128
8.3.2.5 PWM Center Align Enable Register (PWMCAE)
The PWMCAE register contains eight control bits for the selection of center aligned outputs or left aligned
outputs for each PWM channel. If the CAEx bit is set to a one, the corresponding PWM output will be
center aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. See
Section 8.4.2.5, âLeft Aligned Outputsâ and Section 8.4.2.6, âCenter Aligned Outputsâ for a more detailed
description of the PWM output modes.
R
W
Reset
7
CAE7
0
6
CAE6
5
CAE5
4
CAE4
3
CAE3
2
CAE2
0
0
0
0
0
Figure 8-7. PWM Center Align Enable Register (PWMCAE)
1
CAE1
0
0
CAE0
0
MC9S12XDP512 Data Sheet, Rev. 2.21
372
Freescale Semiconductor
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