MC9S12XD256MAL Datasheet, PDF (703/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 19 S12X Debug (S12XDBGV2) Module
19.3.1.7 Debug State Control Registers
Each of the state sequencer states 1 to 3 features a dedicated control register to determine if transitions
from that state are allowed depending upon comparator matches or tag hits and to define the next state for
the state sequencer following a match. The 3 debug state control registers are located at the same address
in the register address map (0x0027). Each register can be accessed using the COMRV bits in DBGC1 to
blend in the required register (see Table 19-19).
Table 19-19. State Control Register Access Encoding
COMRV
00
01
10
11
Visible State Control Register
DBGSCR1
DBGSCR2
DBGSCR3
DBGSCR3
19.3.1.8 Debug State Control Register 1 (DBGSCR1)
0x0027
7
6
5
4
R
0
0
0
0
W
Reset
0
0
0
0
Unimplemented or Reserved
3
SC3
0
2
SC2
0
1
SC1
0
0
SC0
0
Figure 19-10. Debug State Control Register 1 (DBGSCR1)
Read: Anytime
Write: Anytime when DBG not armed.
This register is visible at 0x0027 only with COMRV[1:0] = 00. The state control register 1 selects the
targeted next state while in State1. The matches refer to the match channels of the comparator match
control logic as depicted in Figure 19-1 and described in Section 19.3.1.11.1, “Debug Comparator Control
Register (DBGXCTL)”. Comparators must be enabled by setting the comparator enable bit in the
associated DBGXCTL control register.
Table 19-20. DBGSCR1 Field Descriptions
Field
3–0
SC[3:0}
Description
State Control Bits — These bits select the targeted next state while in State1, based upon the match event.
See Table 19-21.
The trigger priorities described in Table 19-38 dictate that in the case of simultaneous matches, the match on
the lower channel number ([0,1,2,3) has priority. The SC[3:0] encoding ensures that a match leading to final
state has priority over all other matches.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
705