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MC9S12XD256MAL Datasheet, PDF (900/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network | |||
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Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
⢠Control registers to enable/disable pull-device and select pull-ups/pull-downs on Ports T, S, M, P,
H, and J on per-pin basis
⢠Control registers to enable/disable pull-up devices on Ports AD0, and AD1 on per-pin basis
⢠Single control register to enable/disable pull-ups on Ports A, B, C, D, E, and K on per-port basis
and on BKGD pin
⢠Control registers to enable/disable reduced output drive on Ports T, S, M, P, H, J, AD0, and AD1
on per-pin basis
⢠Single control register to enable/disable reduced output drive on Ports A, B, C, D, E, and K on per-
port basis
⢠Control registers to enable/disable open-drain (wired-OR) mode on Ports S and M
⢠Control registers to enable/disable pin interrupts on Ports P, H, and J
⢠Interrupt flag register for pin interrupts on Ports P, H, and J
⢠Control register to configure IRQ pin operation
⢠Free-running clock outputs
A standard port pin has the following minimum features:
⢠Input/output selection
⢠5V output drive with two selectable drive strengths
⢠5V digital and analog input
⢠Input with selectable pull-up or pull-down device
Optional features:
⢠Open drain for wired-OR connections
⢠Interrupt inputs with glitch filtering
⢠Reduced input threshold to support low voltage applications
23.0.2 Block Diagram
Figure 23-1 is a block diagram of the PIM.
⢠Signals shown in Bold are not available in 80-pin packages.
⢠Signals shown in Bold-Italics are neither available in 112-pin nor in 80-pin packages.
⢠Shaded labels denote alternative module routing ports.
MC9S12XDP512 Data Sheet, Rev. 2.21
902
Freescale Semiconductor
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