MC9S12XD256MAL Datasheet, PDF (506/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 11 Serial Communication Interface (S12SCIV5)
In Figure 11-24, a large burst of noise is perceived as the beginning of a start bit, although the test sample
at RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived
bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.
Perceived Start Bit
Actual Start Bit
LSB
RXD
Samples 1 1 1 0
0
1
0000
RT Clock
RT Clock Count
Reset RT Clock
Figure 11-24. Start Bit Search Example 3
Figure 11-25 shows the effect of noise early in the start bit time. Although this noise does not affect proper
synchronization with the start bit time, it does set the noise flag.
Perceived and Actual Start Bit
LSB
RXD
Samples 1 1 1 1 1 1 1 1 1 0
1
0
RT Clock
RT Clock Count
Reset RT Clock
Figure 11-25. Start Bit Search Example 4
MC9S12XDP512 Data Sheet, Rev. 2.21
506
Freescale Semiconductor