MC9S12XD256MAL Datasheet, PDF (996/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2)
24.0.5.9 ECLK Control Register (ECLKCTL)
7
6
5
4
3
R
0
0
0
NECLK NCLKX2
W
Reset¹ Mode
Dependent
1
0
0
0
SS
0
1
0
0
0
ES
1
1
0
0
0
ST
0
1
0
0
0
EX
0
1
0
0
0
NS
1
1
0
0
0
NX
0
1
0
0
0
2
1
0
0
EDIV1
EDIV0
0
0
0
Mode
0
0
0
Special
Single-Chip
0
0
0
Emulation
Single-Chip
0
0
0
Special
Test
0
0
0
Emulation
Expanded
0
0
0
Normal
Single-Chip
0
0
0
Normal
Expanded
= Unimplemented or Reserved
Figure 24-11. ECLK Control Register (ECLKCTL)
1. Reset values in emulation modes are identical to those of the target mode.
Read: Anytime.
Write: Anytime.
The ECLKCTL register is used to control the availability of the free-running clocks and the free-running
clock divider.
Table 24-12. ECLKCTL Field Descriptions
Field
Description
7
NECLK
6
NCLKX2
1–0
EDIV[1:0]
No ECLK — This bit controls the availability of a free-running clock on the ECLK pin. Clock output is always
active in emulation modes and if enabled in all other operating modes.
0 ECLK enabled
1 ECLK disabled
No ECLKX2 — This bit controls the availability of a free-running clock on the ECLKX2 pin. This clock has a fixed
rate of twice the internal bus clock. Clock output is always active in emulation modes and if enabled in all other
operating modes.
0 ECLKX2 is enabled
1 ECLKX2 is disabled
Free-Running ECLK Divider — These bits determine the rate of the free-running clock on the ECLK pin. The
usage of the bits is shown in Table 24-13. Divider is always disabled in emulation modes and active as
programmed in all other operating modes.
MC9S12XDP512 Data Sheet, Rev. 2.21
998
Freescale Semiconductor