MC9S12XD256MAL Datasheet, PDF (1274/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Appendix A Electrical Characteristics
In Table A-26 the timing characteristics for master mode are listed.
Table A-26. SPI Master Mode Timing Characteristics
Num
1
1
2
3
4
5
6
9
10
11
12
13
C
Characteristic
D SCK frequency
D SCK period
D Enable lead time
D Enable lag time
D Clock (SCK) high or low time
D Data setup time (inputs)
D Data hold time (inputs)
D Data valid after SCK edge
D Data valid after SS fall (CPHA = 0)
D Data hold time (outputs)
D Rise and fall time inputs
D Rise and fall time outputs
Symbol
Min
Typ
f_sck
1/2048
—
t_sck
2
—
t_lead
—
1/2
t_lag
—
1/2
t_wsck
—
1/2
t_su
8
—
t_hi
8
—
t_vsck
—
—
t_vss
—
—
t_ho
0
—
t_rfi
—
—
t_rfo
—
—
Max
1/2
2048
—
—
—
—
—
15
15
—
8
8
Unit
f_bus
t_bus
t_sck
t_sck
t_sck
ns
ns
ns
ns
ns
ns
ns
f_SCK/f_bus
Figure A-8. Derating of maximum f_SCK to f_bus ratio in Master Mode
1/2
1/4
5
10 ¹⁵ 20 ²⁵ 30 ³⁵ 40
f_bus [MHz]
In Master Mode the allowed maximum f_SCK to f_bus ratio (= minimum Baud Rate Divisor, pls. see
SPI Section) derates with increasing f_bus.
A.7.2 Slave Mode
In Figure A-9 the timing diagram for slave mode with transmission format CPHA = 0 is depicted.
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MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor