MC9S12XD256MAL Datasheet, PDF (368/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 8 Pulse-Width Modulator (S12PWM8B8CV1)
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
PWMPER7 R
Bit 7
6
5
4
3
2
1
Bit 0
W
PWMDTY0 R
Bit 7
6
5
4
3
2
1
Bit 0
W
PWMDTY1 R
Bit 7
6
5
4
3
2
1
Bit 0
W
PWMDTY2 R
Bit 7
6
5
4
3
2
1
Bit 0
W
PWMDTY3 R
Bit 7
6
5
4
3
2
1
Bit 0
W
PWMDTY4 R
Bit 7
6
5
4
3
2
1
Bit 0
W
PWMDTY5 R
Bit 7
6
5
4
3
2
1
Bit 0
W
PWMDTY6 R
Bit 7
6
5
4
3
2
1
Bit 0
W
PWMDTY7 R
Bit 7
6
5
4
3
2
1
Bit 0
W
PWMSDN R
0
0
PWM7IN
PWMIF
PWMIE
PWMLVL
PWM7INL PWM7ENA
W
PWMRSTRT
= Unimplemented or Reserved
Figure 8-2. PWM Register Summary (Sheet 3 of 3)
1 _{Intended for factory test purposes only.}
8.3.2.1 PWM Enable Register (PWME)
Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx
bits are set (PWMEx = 1), the associated PWM output is enabled immediately. However, the actual PWM
waveform is not available on the associated PWM output until its clock source begins its next cycle due to
the synchronization of PWMEx and the clock source.
NOTE
The first PWM cycle after enabling the channel can be irregular.
An exception to this is when channels are concatenated. Once concatenated mode is enabled (CONxx bits
set in PWMCTL register), enabling/disabling the corresponding 16-bit PWM channel is controlled by the
MC9S12XDP512 Data Sheet, Rev. 2.21
368
Freescale Semiconductor