MC9S12XD256MAL Datasheet, PDF (654/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 18 Memory Mapping Control (S12XMMCV3)
18.1.4.2 Functional Modes
• Single chip modes
In normal and special single chip mode the internal memory is used. External bus is not active.
• Expanded modes
Address, data, and control signals are activated in normal expanded and special test modes when
accessing the external bus. Access to internal resources will not cause activity on the external bus.
• Emulation modes
External bus is active to emulate, via an external tool, the normal expanded or the normal single
chip mode.
18.1.5 Block Diagram
Figure 18-1¹ shows a block diagram of the MMC.
EEPROM
FLASH
BDM
CPU
XGATE
MMC
Address Decoder & Priority
FLEXRAY
DBG
Target Bus Controller
EBI
RAM
Peripherals
Figure 18-1. MMC Block Diagram
18.2 External Signal Description
The user is advised to refer to the SoC Guide for port configuration and location of external bus signals.
Some pins may not be bonded out in all implementations.
Table 18-2 and Table 18-3 outline the pin names and functions. It also provides a brief description of their
operation.
1. Doted blocks and lines are optional. Please refer to the Device User Guide for their availlibilities.
MC9S12XDP512 Data Sheet, Rev. 2.21
654
Freescale Semiconductor