MC9S12XD256MAL Datasheet, PDF (204/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 6 XGATE (S12XGATEV2)
6.4.4 Semaphores
The XGATE module offers a set of eight hardware semaphores. These semaphores provide a mechanism
to protect system resources that are shared between two concurrent threads of program execution; one
thread running on the S12X_CPU and one running on the XGATE RISC core.
Each semaphore can only be in one of the three states: “Unlocked”, “Locked by S12X_CPU”, and “Locked
by XGATE”. The S12X_CPU can check and change a semaphore’s state through the XGATE semaphore
register (XGSEM, see Section 6.3.1.6, “XGATE Semaphore Register (XGSEM)”). The RISC core does
this through its SSEM and CSEM instructions.
Figure 6-21 illustrates the valid state transitions.
%1 ⇒ XGSEM
SSEM Instruction
CSEM Instruction
%1 ⇒ XGSEM
%0 ⇒ XGSEM
SSEM Instruction
LOCKED BY
LOCKED BY
S12X_CPU
XGATE
%0 _⇒
an%d _S1S⇒^%EM1XG⇒_{IonSrsXEtrGM. SEMXGSEMUNLOCKED}
CInSsEtrMuctSIinoSsnEtruMction
%0 ⇒ XGSEM
CSEM Instruction
Figure 6-21. Semaphore State Transitions
MC9S12XDP512 Data Sheet, Rev. 2.21
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