MC9S12XD256MAL Datasheet, PDF (723/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 19 S12X Debug (S12XDBGV2) Module
19.4.5.3.1 Information Byte Organization
The format of the control information byte for both CPU and XGATE modules is dependent upon the
active trace mode and tracing source as described below. In normal mode or loop1 mode, tracing of
XGATE activity XINF is used to store control information. In normal mode or loop1 mode, tracing of CPU
activity CINF is used to store control information. In detail mode, CXINF contains the control information.
Bit 7
XSD
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
0
XDV
0
0
Figure 19-24. XGATE Information Byte XINF
Bit 1
0
Bit 0
0
Table 19-40. XINF Field Descriptions
Field
7
XSD
4
XDV
Description
Source Destination Indicator — This bit indicates if the corresponding stored address is a source or
destination address. This is only used in normal and loop1 mode tracing.
0 Source Address
1 Destination Address
Data Invalid Indicator — This bit indicates if the trace buffer entry is invalid. It is only used when tracing from
both sources in normal and loop1 mode, to indicate that the XGATE trace buffer entry is valid.
0 Trace buffer entry is invalid
1 Trace buffer entry is valid
Bit 7
CSD
Bit 6
0
Bit 5
Bit 4
Bit 3
Bit 2
0
CDV
0
0
Figure 19-25. CPU Information Byte CINF
Bit 1
0
Bit 0
0
Table 19-41. CINF Field Descriptions
Field
7
CSD
4
CDV
Description
Source Destination Indicator — This bit indicates if the corresponding stored address is a source or
destination address. This is only used in normal and loop1 mode tracing.
0 Source Address
1 Destination Address
Data Invalid Indicator — This bit indicates if the trace buffer entry is invalid. It is only used when tracing from
both sources in normal and loop1 mode, to indicate that the CPU trace buffer entry is valid.
0 Trace buffer entry is invalid
1 Trace buffer entry is valid
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
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