MC9S12XD256MAL Datasheet, PDF (272/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 6 XGATE (S12XGATEV2)
ROR
Rotate Right
ROR
Operation
RD
n bits
n = RS or IMM4
Rotates the bits in register RD n positions to the right. The upper n bits of the register RD are filled with
the lower n bits. Two source forms are available. In the first form, the parameter n is contained in the
instruction code as an immediate operand. In the second form, the parameter is contained in the lower bits
of the source register RS[3:0]. All other bits in RS are ignored. If n is zero no shift will take place and the
register RD will be unaffected; however, the condition code flags will be updated.
CCR Effects
NZVC
∆ ∆ 0—
N: Set if bit 15 of the result is set; cleared otherwise.
Z: Set if the result is $0000; cleared otherwise.
V: 0; cleared.
C: Not affected.
Code and CPU Cycles
Source Form
ROR RD, #IMM4
ROR RD, RS
Address
Mode
IMM4
DYA
00001
00001
Machine Code
Cycles
RD
IMM4
1111
P
RD
RS 1 0 1 1 1
P
MC9S12XDP512 Data Sheet, Rev. 2.21
272
Freescale Semiconductor