MC9S12XD256MAL Datasheet, PDF (357/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
7.4.1 Enhanced Capture Timer Modes of Operation
The enhanced capture timer has 8 input capture, output compare (IC/OC) channels, same as on the HC12
standard timer (timer channels TC0 to TC7). When channels are selected as input capture by selecting the
IOSx bit in TIOS register, they are called input capture (IC) channels.
Four IC channels (channels 7–4) are the same as on the standard timer with one capture register each that
memorizes the timer value captured by an action on the associated input pin.
Four other IC channels (channels 3–0), in addition to the capture register, also have one buffer each called
a holding register. This allows two different timer values to be saved without generating any interrupts.
Four 8-bit pulse accumulators are associated with the four buffered IC channels (channels 3–0). Each pulse
accumulator has a holding register to memorize their value by an action on its external input. Each pair of
pulse accumulators can be used as a 16-bit pulse accumulator.
The 16-bit modulus down-counter can control the transfer of the IC registers and the pulse accumulators
contents to the respective holding registers for a given period, every time the count reaches zero.
The modulus down-counter can also be used as a stand-alone time base with periodic interrupt capability.
7.4.1.1 IC Channels
The IC channels are composed of four standard IC registers and four buffered IC channels.
• An IC register is empty when it has been read or latched into the holding register.
• A holding register is empty when it has been read.
7.4.1.1.1 Non-Buffered IC Channels
The main timer value is memorized in the IC register by a valid input pin transition. If the corresponding
NOVWx bit of the ICOVW register is cleared, with a new occurrence of a capture, the contents of IC
register are overwritten by the new value. If the corresponding NOVWx bit of the ICOVW register is set,
the capture register cannot be written unless it is empty. This will prevent the captured value from being
overwritten until it is read.
7.4.1.1.2 Buffered IC Channels
There are two modes of operations for the buffered IC channels:
1. IC latch mode (LATQ = 1)
The main timer value is memorized in the IC register by a valid input pin transition (see Figure 7-65
and Figure 7-66).
The value of the buffered IC register is latched to its holding register by the modulus counter for a
given period when the count reaches zero, by a write 0x0000 to the modulus counter or by a write
to ICLAT in the MCCTL register.
If the corresponding NOVWx bit of the ICOVW register is cleared, with a new occurrence of a
capture, the contents of IC register are overwritten by the new value. In case of latching, the
contents of its holding register are overwritten.
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
357