MC9S12XD256MAL Datasheet, PDF (997/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Table 24-13. Free-Running ECLK Clock Rate
EDIV[1:0]
00
01
10
11
Rate of Free-Running ECLK
ECLK = Bus clock rate
ECLK = Bus clock rate divided by 2
ECLK = Bus clock rate divided by 3
ECLK = Bus clock rate divided by 4
24.0.5.10 IRQ Control Register (IRQCR)
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
IRQE
IRQEN
W
Reset
0
1
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 24-12. IRQ Control Register (IRQCR)
Read: See individual bit descriptions below.
Write: See individual bit descriptions below.
Table 24-14. IRQCR Field Descriptions
Field
7
IRQE
6
IRQEN
Description
IRQ Select Edge Sensitive Only
Special modes: Read or write anytime.
Normal and emulation modes: Read anytime, write once.
0 IRQ configured for low level recognition.
1 IRQ configured to respond only to falling edges. Falling edges on the IRQ pin will be detected anytime
IRQE = 1 and will be cleared only upon a reset or the servicing of the IRQ interrupt.
External IRQ Enable
Read or write anytime.
0 External IRQ pin is disconnected from interrupt logic.
1 External IRQ pin is connected to interrupt logic.
24.0.5.11 Port K Data Register (PORTK)
7
6
5
4
3
2
1
0
R
0
PK7
PK5
PK4
PK3
PK2
PK1
PK0
W
Reset
0
0
0
0
0
0
0
0
Figure 24-13. Port K Data Register (PORTK)
Read: Anytime.
Write: Anytime.