MC9S12XD256MAL Datasheet, PDF (576/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 15 Background Debug Module (S12XBDMV2)
Table 15-3. BDM Clock Sources
PLLSEL CLKSW
BDMCLK
0
0
Bus clock dependent on oscillator
0
1
Bus clock dependent on oscillator
1
0
Alternate clock (refer to the device specification to determine the alternate clock source)
1
1
Bus clock dependent on the PLL
15.3.2.2 BDM CCR LOW Holding Register (BDMCCRL)
Register Global Address 0x7FFF06
7
R
CCR7
W
6
CCR6
5
CCR5
4
CCR4
3
CCR3
2
CCR2
Reset
Special Single-Chip Mode
1
1
0
0
1
0
All Other Modes
0
0
0
0
0
0
Figure 15-4. BDM CCR LOW Holding Register (BDMCCRL)
1
CCR1
0
0
0
CCR0
0
0
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
NOTE
When BDM is made active, the CPU stores the content of its CCR_L register
in the BDMCCRL register. However, out of special single-chip reset, the
BDMCCRL is set to 0xD8 and not 0xD0 which is the reset value of the
CCR_L register in this CPU mode. Out of reset in all other modes the
BDMCCRL register is read zero.
When entering background debug mode, the BDM CCR LOW holding register is used to save the low byte
of the condition code register of the user’s program. It is also used for temporary storage in the standard
BDM firmware mode. The BDM CCR LOW holding register can be written to modify the CCR value.
MC9S12XDP512 Data Sheet, Rev. 2.21
576
Freescale Semiconductor