MC9S12XD256MAL Datasheet, PDF (795/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

21.4.2.2.2 Write Access Timing
Chapter 21 External Bus Interface (S12XEBIV2)
Table 21-12. Write Access (1 Cycle)
Access #0
Access #1
Access #2
Bus cycle ->
...
1
2
3
...
ECLK phase
... high
low
high
low
high
low ...
ADDR[22:20] / ACC[2:0] ...
acc 0
acc 1
acc 2 ...
ADDR[19:16] / IQSTAT[3:0] ... addr 0 iqstat -1 addr 1 iqstat 0 addr 2 iqstat 1 ...
ADDR[15:0] / IVD[15:0] ...
?
x
x ...
DATA[15:0] (write)
... ?
data 0
data 1
data 2 ...
R/W
... 0
0
1
1
1
1 ...
Table 21-13. Write Access (2 Cycles)
Access #0
Access #1
Bus cycle ->
...
1
2
3
...
ECLK phase
... high
low
high
low
high
low ...
ADDR[22:20] / ACC[2:0] ...
acc 0
000
acc 1 ...
ADDR[19:16] / IQSTAT[3:0] ... addr 0 iqstat-1 addr 0 iqstat 0 addr 1 0000 ...
ADDR[15:0] / IVD[15:0] ...
?
x
x ...
DATA[15:0] (write)
... ?
data 0
x ...
R/W
... 0
0
0
0
1
1 ...
Table 21-14. Write Access (n–1 Cycles)
Access #0
Access #1
Bus cycle ->
...
1
2
3
...
n
...
ECLK phase
... high
low
high
low
high
low ... high
low ...
ADDR[22:20] / ACC[2:0] ...
acc 0
000
000 ...
acc 1 ...
ADDR[19:16] / IQSTAT[3:0] ... addr 0 iqstat-1 addr 0 iqstat 0 addr 0 0000 ... addr 1 0000 ...
ADDR[15:0] / IVD[15:0] ...
?
x
x ...
x ...
DATA[15:0] (write)
... ?
data 0
x ...
R/W
... 0
0
0
0
0
0 ... 1
1 ...
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
797