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MC9S12XD256MAL Datasheet, PDF (100/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network
Chapter 2 Clocks and Reset Generator (S12CRGV6)
The following conditions apply when the PLL is in automatic bandwidth control mode (AUTO = 1):
• The TRACK bit is a read-only indicator of the mode of the filter.
• The TRACK bit is set when the VCO frequency is within a certain tolerance, ∆trk, and is clear when
the VCO frequency is out of a certain tolerance, ∆unt.
• The LOCK bit is a read-only indicator of the locked state of the PLL.
• The LOCK bit is set when the VCO frequency is within a certain tolerance, ∆Lock, and is cleared
when the VCO frequency is out of a certain tolerance, ∆unl.
• Interrupt requests can occur if enabled (LOCKIE = 1) when the lock condition changes, toggling
the LOCK bit.
The PLL can also operate in manual mode (AUTO = 0). Manual mode is used by systems that do not
require an indicator of the lock condition for proper operation. Such systems typically operate well below
the maximum system frequency (fsys) and require fast start-up. The following conditions apply when in
manual mode:
• ACQ is a writable control bit that controls the mode of the filter. Before turning on the PLL in
manual mode, the ACQ bit should be asserted to configure the filter in acquisition mode.
• After turning on the PLL by setting the PLLON bit software must wait a given time (tacq) before
entering tracking mode (ACQ = 0).
• After entering tracking mode software must wait a given time (tal) before selecting the PLLCLK
as the source for system and core clocks (PLLSEL = 1).
2.4.1.2 System Clocks Generator
PLLSEL or SCM
PHASE
LOCK
LOOP
PLLCLK
1
0
STOP
SYSCLK
CORE CLOCK
EXTAL
OSCCLK
OSCILLATOR
XTAL
÷2
SCM
WAIT(RTIWAI),
STOP(PSTP,PRE),
1
RTI ENABLE
0
WAIT(COPWAI),
STOP(PSTP,PCE),
COP ENABLE
GATING
CONDITION
CLOCK
MONITOR
STOP
= CLOCK GATE
Figure 2-17. System Clocks Generator
CLOCK PHASE
GENERATOR
RTI
COP
BUS CLOCK
OSCILLATOR
CLOCK
MC9S12XDP512 Data Sheet, Rev. 2.21
100
Freescale Semiconductor