MC9S12XD256MAL Datasheet, PDF (1164/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1)
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 28-22. RESERVED3
All bits read 0 and are not writable.
28.3.2.14 RESERVED4
This register is reserved for factory testing and is not accessible.
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 28-23. RESERVED4
All bits read 0 and are not writable.
28.4 Functional Description
28.4.1 Flash Command Operations
Write operations are used to execute program, erase, erase verify, erase abort, and data compress
algorithms described in this section. The program and erase algorithms are controlled by a state machine
whose timebase, FCLK, is derived from the oscillator clock via a programmable divider. The command
register, as well as the associated address and data registers, operate as a buffer and a register (2-stage
FIFO) so that a second command along with the necessary data and address can be stored to the buffer
while the first command is still in progress. This pipelined operation allows a time optimization when
programming more than one word on a specific row in the Flash block as the high voltage generation can
be kept active in between two programming commands. The pipelined operation also allows a
simplification of command launching. Buffer empty as well as command completion are signalled by flags
in the Flash status register with corresponding interrupts generated, if enabled.
The next sections describe:
1. How to write the FCLKDIV register
2. Command write sequences to program, erase, erase verify, erase abort, and data compress
operations on the Flash memory
3. Valid Flash commands
4. Effects resulting from illegal Flash command write sequences or aborting Flash operations
1166
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor