MC9S12XD256MAL Datasheet, PDF (1172/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 28 256 Kbyte Flash Module (S12XFTX256K2V1)
START
Read: FCLKDIV register
Clock Register
Written
Check
FDIVLD
Set?
yes
no
Write: FCLKDIV register
NOTE: FCLKDIV needs to
be set once after each reset.
Read: FSTAT register
Address, Data,
Command
Buffer Empty Check
CBEIF
no
Set?
yes
Access Error and
Protection Violation
Check
1.
ACCERR/
yes
PVIOL
Set?
no
Write: Flash Address to start
compression and number of word
addresses to compress
Simultaneous
Multiple Flash Block
Decision
2.
Next
yes
Flash
Block?
no
Write: FCMD register
Data Compress Command 0x06
Write: FSTAT register
Clear ACCERR/PVIOL 0x30
NOTE: address used to select
Flash block; data ignored.
Decrement Global Address
by 128K (skip unimplemented Flash)
3.
Write: FSTAT register
Clear CBEIF 0x80
Read: FSTAT register
Bit Polling for
Command Completion
Check
CCIF
no
Set?
yes
Read: FDATA registers
Data Compress Signature
Signature
no
Valid?
yes
EXIT
Erase and Reprogram
Flash Sector(s) Compressed
Figure 28-26. Example Data Compress Command Flow
1174
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor