MC9S12XD256MAL Datasheet, PDF (164/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 5 Analog-to-Digital Converter (S12ATD10B8CV2)
Register
Name
ATDDR3L
ATDDR4H
ATDDR4L
ATDD45H
ATDD45L
ATDD46H
ATDDR6L
ATDD47H
ATDD47L
Bit 7
10-BIT
8-BIT
W
BIT 1
U
10-BIT BIT 9 MSB
8-BIT BIT 7 MSB
W
10-BIT
8-BIT
W
BIT 1
U
10-BIT BIT 9 MSB
8-BIT BIT 7 MSB
W
10-BIT
8-BIT
W
BIT 1
U
10-BIT BIT 9 MSB
8-BIT BIT 7 MSB
W
10-BIT
8-BIT
W
BIT 1
U
10-BIT BIT 9 MSB
8-BIT BIT 7 MSB
W
10-BIT
8-BIT
W
BIT 1
U
6
BIT 0
U
BIT 8
BIT 6
BIT 0
U
BIT 8
BIT 6
BIT 0
U
BIT 8
BIT 6
BIT 0
U
BIT 8
BIT 6
BIT 0
U
5
0
0
BIT 7
BIT 5
0
0
BIT 7
BIT 5
0
0
BIT 7
BIT 5
0
0
BIT 7
BIT 5
0
0
4
0
0
BIT 6
BIT 4
0
0
BIT 6
BIT 4
0
0
BIT 6
BIT 4
0
0
BIT 6
BIT 4
0
0
3
0
0
BIT 5
BIT 3
0
0
BIT 5
BIT 3
0
0
BIT 5
BIT 3
0
0
BIT 5
BIT 3
0
0
2
0
0
BIT 4
BIT 2
0
0
BIT 4
BIT 2
0
0
BIT 4
BIT 2
0
0
BIT 4
BIT 2
0
0
1
0
0
BIT 3
BIT 1
0
0
BIT 3
BIT 1
0
0
BIT 3
BIT 1
0
0
BIT 3
BIT 1
0
0
Bit 0
0
0
BIT 2
BIT 0
0
0
BIT 2
BIT 0
0
0
BIT 2
BIT 0
0
0
BIT 2
BIT 0
0
0
Right Justified Result Data
Note: The read portion of the right justified result data registers has been divided to show the bit position when reading 10-bit
and 8-bit conversion data. For more detailed information refer to Section 5.3.2.13, “ATD Conversion Result Registers
(ATDDRx)”.
ATDDR0H
10-BIT
0
0
0
0
0
0
BIT 9 MSB BIT 8
8-BIT
0
0
0
0
0
0
0
0
W
ATDDR0L
10-BIT BIT 7
8-BIT BIT 7 MSB
W
BIT 6
BIT 6
BIT 5
BIT 5
BIT 4
BIT 4
BIT 3
BIT 3
BIT 2
BIT 2
BIT 1
BIT 1
BIT 0
BIT 0
= Unimplemented or Reserved
Figure 5-2. ATD Register Summary (Sheet 3 of 5)
MC9S12XDP512 Data Sheet, Rev. 2.21
164
Freescale Semiconductor