MC9S12XD256MAL Datasheet, PDF (328/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 7 Enhanced Capture Timer (S12ECT16B8CV2)
7.3.2.12 Main Timer Interrupt Flag 1 (TFLG1)
7
R
C7F
W
6
C6F
5
C5F
4
C4F
3
C3F
2
C2F
1
C1F
0
C0F
Reset
0
0
0
0
0
0
0
0
Figure 7-17. Main Timer Interrupt Flag 1 (TFLG1)
Read: Anytime
Write used in the flag clearing mechanism. Writing a one to the flag clears the flag. Writing a zero will not
affect the current status of the bit.
NOTE
When TFFCA = 1, the flags cannot be cleared via the normal flag clearing
mechanism (writing a one to the flag). Reference Section 7.3.2.6, “Timer
System Control Register 1 (TSCR1)”.
All bits reset to zero.
TFLG1 indicates when interrupt conditions have occurred. The flags can be cleared via the normal flag
clearing mechanism (writing a one to the flag) or via the fast flag clearing mechanism (reference TFFCA
bit in Section 7.3.2.6, “Timer System Control Register 1 (TSCR1)”).
Use of the TFMOD bit in the ICSYS register in conjunction with the use of the ICOVW register allows a
timer interrupt to be generated after capturing two values in the capture and holding registers, instead of
generating an interrupt for every capture.
Table 7-16. TFLG1 Field Descriptions
Field
7:0
C[7:0]F
Description
Input Capture/Output Compare Channel “x” Flag — A CxF flag is set when a corresponding input capture or
output compare is detected. C0F can also be set by 16-bit Pulse Accumulator B (PACB). C3F–C0F can also be
set by 8-bit pulse accumulators PAC3–PAC0.
If the delay counter is enabled, the CxF flag will not be set until after the delay.
MC9S12XDP512 Data Sheet, Rev. 2.21
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