MC9S12XD256MAL Datasheet, PDF (920/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
Table 23-6. DDRA Field Descriptions
Field
Description
7–0
DDRA[7:0]
Data Direction Port A — This register controls the data direction for port A. When Port A is operating as a general
purpose I/O port, DDRA determines whether each pin is an input or output. A logic level “1” causes the
associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PORTA after changing the DDRA register.
23.0.5.4 Port B Data Direction Register (DDRB)
7
R
DDRB7
W
6
DDRB6
5
DDRB5
4
DDRB4
3
DDRB3
2
DDRB2
1
DDRB1
0
DDRB0
Reset
0
0
0
0
0
0
0
0
Figure 23-6. Port B Data Direction Register (DDRB)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 23-7. DDRB Field Descriptions
Field
Description
7–0
DDRB[7:0]
Data Direction Port B — This register controls the data direction for port B. When Port B is operating as a general
purpose I/O port, DDRB determines whether each pin is an input or output. A logic level “1” causes the
associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PORTB after changing the DDRB register.
23.0.5.5 Port C Data Register (PORTC)
7
R
PC7
W
6
PC6
5
PC5
4
PC4
3
PC3
2
PC2
1
PC1
0
PC0
Reset
0
0
0
0
0
0
0
0
Figure 23-7. Port C Data Register (PORTC)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
MC9S12XDP512 Data Sheet, Rev. 2.21
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Freescale Semiconductor