MC9S12XD256MAL Datasheet, PDF (755/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 20 S12X Debug (S12XDBGV3) Module
20.3.2.6 Debug Count Register (DBGCNT)
Address: 0x0026
7
6
5
4
3
2
1
0
R
0
CNT
W
Reset
0
POR
0
—
—
—
—
—
—
—
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 20-8. Debug Count Register (DBGCNT)
Read: Anytime
Write: Never
Table 20-17. DBGCNT Field Descriptions
Field
6–0
CNT[6:0]
Description
Count Value — The CNT bits [6:0] indicate the number of valid data 64-bit data lines stored in the Trace Buffer.
Table 20-18 shows the correlation between the CNT bits and the number of valid data lines in the Trace Buffer.
When the CNT rolls over to zero, the TBF bit in DBGSR is set and incrementing of CNT will continue in
end-trigger or mid-trigger mode. The DBGCNT register is cleared when ARM in DBGC1 is written to a one. The
DBGCNT register is cleared by power-on-reset initialization but is not cleared by other system resets. Thus
should a reset occur during a debug session, the DBGCNT register still indicates after the reset, the number of
valid trace buffer entries stored before the reset occurred. The DBGCNT register is not decremented when
reading from the trace buffer.
Table 20-18. CNT Decoding Table
TBF (DBGSR)
CNT[6:0]
Description
0
0000000
0
0000001
No data valid
32 bits of one line valid¹
0
0000010
0000100
0000110
..
1111100
1 line valid
2 lines valid
3 lines valid
..
62 lines valid
0
1111110
63 lines valid
1
0000000
64 lines valid; if using Begin trigger alignment,
ARM bit will be cleared and the tracing session ends.
1
0000010
64 lines valid,
..
oldest data has been overwritten by most recent data
..
1111110
1 _{This applies to Normal/Loop1 Modes when tracing from either S12XCPU or XGATE only.}
MC9S12XDP512 Data Sheet, Rev. 2.21
Freescale Semiconductor
757