MC9S12XD256MAL Datasheet, PDF (1019/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

24.0.5.51 Port J Input Register (PTIJ)
7
6
5
4
3
2
1
0
R PTIJ7
PTIJ6
0
0
0
0
PTIJ1
PTIJ0
W
Reset¹
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 24-53. Port J Input Register (PTIJ)
1. These registers are reset to zero. Two bus clock cycles after reset release the register values are updated with the
associated pin values.
Read: Anytime.
Write: Never, writes to this register have no effect.
This register always reads back the buffered state of the associated pins. This can be used to detect
overload or short circuit conditions on output pins.
24.0.5.52 Port J Data Direction Register (DDRJ)
7
6
5
4
3
2
1
0
R
0
0
0
0
DDRJ7
DDRJ6
DDRJ1
DDRJ0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 24-54. Port J Data Direction Register (DDRJ)
Read: Anytime.
Write: Anytime.
This register configures each port J pin (except PJ5-2) as either input or output.
The CAN forces the I/O state to be an output on PJ7 (TXCAN4) and an input on pin PJ6
(RXCAN4). The IIC takes control of the I/O if enabled. In these cases the data direction bits will
not change.
The DDRJ bits revert to controlling the I/O direction of a pin when the associated peripheral
module is disabled.
Table 24-48. DDRJ Field Descriptions
Field
Description
7–0
DDRJ[7:6]
DDRJ[1:0]
Data Direction Port J
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note: Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PTJ or PTIJ registers, when changing the DDRJ register.