MC9S12XD256MAL Datasheet, PDF (918/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
PER1AD0 R
PER1AD07 PER1AD06 PER1AD05 PER1AD04 PER1AD03 PER1AD02 PER1AD01 PER1AD00
W
PT0AD1 R
PT0AD123 PT0AD122 PT0AD121 PT0AD120 PT0AD119 PT0AD118 PT0AD117 PT0AD116
W
PT1AD1 R
PT1AD115 PT1AD114 PT1AD113 PT1AD112 PT1AD111 PT1AD110 PT1AD19
W
PT1AD18
DDR0AD1 R
DDR0AD123 DDR0AD122 DDR0AD121 DDR0AD120 DDR0AD119 DDR0AD118 DDR0AD117 DDR0AD116
W
DDR1AD1 R
DDR1AD115 DDR1AD114 DDR1AD113 DDR1AD112 DDR1AD111 DDR1AD110 DDR1AD19 DDR1AD18
W
RDR0AD1 R
RDR0AD123 RDR0AD122 RDR0AD121 RDR0AD120 RDR0AD119 RDR0AD118 RDR0AD117 RDR0AD116
W
RDR1AD1 R
RDR1AD115 RDR1AD114 RDR1AD113 RDR1AD112 RDR1AD111 RDR1AD110 RDR1AD19 RDR1AD18
W
PER0AD1 R
PER0AD123 PER0AD122 PER0AD121 PER0AD120 PER0AD119 PER0AD118 PER0AD117 PER0AD116
W
PER1AD1 R
PER1AD115 PER1AD114 PER1AD113 PER1AD112 PER1AD111 PER1AD110 PER1AD19 PER1AD18
W
23.0.5.1
= Unimplemented or Reserved
Port A Data_FR_ige_ug_reis₂₃te_-2r_{. P}(P_IMO_RR_eT_gA_ist)_{er Summary (Sheet 7 of 7)}
R
W
Alt.
Function
Reset
7
PA7
ADDR15
mux
IVD15
0
6
5
4
3
2
PA6
PA5
PA4
PA3
PA2
ADDR14
mux
IVD14
ADDR13
mux
IVD13
ADDR12
mux
IVD12
ADDR11
mux
IVD11
ADDR10
mux
IVD10
0
0
0
0
0
Figure 23-3. Port A Data Register (PORTA)
1
PA1
ADDR9
mux
IVD9
0
0
PA0
ADDR8
mux
IVD8
0
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
MC9S12XDP512 Data Sheet, Rev. 2.21
920
Freescale Semiconductor