MC9S12XD256MAL Datasheet, PDF (858/1348 Pages) Freescale Semiconductor, Inc – Freescale’s Scalable Controller Area Network

Chapter 22 DP512 Port Integration Module (S12XDP512PIMV2)
22.3.2.45 Port P Interrupt Flag Register (PIFP)
R
W
Reset
7
PIFP7
0
6
PIFP6
5
PIFP5
4
PIFP4
3
PIFP3
2
PIFP2
0
0
0
0
0
Figure 22-47. Port P Interrupt Flag Register (PIFP)
1
PIFP1
0
0
PIFP0
0
Read: Anytime.
Write: Anytime.
Each flag is set by an active edge on the associated input pin. This could be a rising or a falling edge based
on the state of the PPSP register. To clear this flag, write logic level “1” to the corresponding bit in the
PIFP register. Writing a “0” has no effect.
Table 22-44. PIFP Field Descriptions
Field
Description
7–0
PIFP[7:0]
Interrupt Flags Port P
0 No active edge pending. Writing a “0” has no effect.
1 Active edge on the associated bit has occurred (an interrupt will occur if the associated enable bit is set).
Writing a logic level “1” clears the associated flag.
MC9S12XDP512 Data Sheet, Rev. 2.21
860
Freescale Semiconductor